As a conventional semiconductor integrated circuit having a gate bias circuit which renders the operating current constant irrespective of manufacture tolerances, the configuration shown in FIG. 5 is disclosed in e.g., JP Patent Kokai JP-A-6-334445. Referring to FIG. 5, a second field-effect transistor FET 2, manufactured by the same process as the process for fabricating a first field-effect transistor FET 1 used for amplification, having the same structure as the first FET and having a smaller total gate width, is arranged in a gate bias circuit in the same chip with the first FET. The gate bias circuit is configured so that a voltage value determined by a drain current Id22 of the second FET 2 and a resistance value connected to a source terminal of the second FET 2 will be applied to the gate bias terminal of the first FET 1.
The operation is hereinafter explained.
If a transistor is manufactured so that there flows a current Id2 of a large magnitude, more current flows in resistor R2 to produce a significant voltage drop Vg1. This voltage drop is negatively fed back to the first FET 1 to manage control so that the current Id1 will be constant.